1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a BiCMOS semiconductor device including bipolar transistors and MOS transistors.
2. Description of Related Art
For a BiCMOS semiconductor device including bipolar transistors and MOS transistors formed in a mixed condition on the same substrate, various manufacturing methods have been proposed in the prior art.
Here, with reference to the drawings, two examples of the prior art generic manufacturing methods will be described (a first one of which will be called a "first prior art method" and a second one of which will be called a "second prior art method", hereinafter).
First Prior Art Method
FIGS. 3A to 3D are diagrammatic sectional views of a semiconductor device for illustrating the first prior art method for manufacturing the BiCMOS semiconductor device.
In the first prior art method, as shown in FIG. 3A, after an insulator film 2 for a device isolation is formed in a predetermined area on a semiconductor substrate 1 (of for example a P-type) 1, first, a collector region 3, a base region 5 and an n.sup.+ region 4 of a high impurity concentration for leading out the collector region 3, are formed in the semiconductor substrate 1, and then, a P-well 7 arid an N-well (not shown) are formed.
Thereafter, an insulating film 6 is formed on the whole surface of the semiconductor substrate 1. This insulating film 6 will become a gate oxide film, and is formed by a thermal oxidation.
Then, as shown in FIG. 3B, a first polysilicon film 8 is formed on the whole surface of the semiconductor substrate 1, and by a phlotolithography using a photoresist (not shown), an opening is formed to penetrate through the first polysilicon film 8 and two insulating film 6 at a predetermined position above the base region 5 so as to expose a portion of the base region 5. Succeedingly, a second polysilicon film 9 is formed on the whole surface including the opening thus formed, and an n-type impurity (for example, As) is introduced into the second polysilicon film 9.
Thereafter, the second polysilicon film 9 of the n type and the first polysilicon film 8 are patterned to be left in only respective predetermined areas of a MOS transistor formation area and a bipolar transistor formation area, so that a gate and an emitter are constituted.
Furthermore, sidewall insulator films 10 and another insulating film 11 are formed as shown in FIG. 3C, and then, p.sup.- regions (not shown) and p.sup.+ regions (not shown) which constitute source/drain regions of a pMOS transistor and n.sup.- regions 13 and n.sup.+ regions 12 which constitute source/drain regions of an nMOS transistor are formed. In addition, a p.sup.+ region 14 constituting a graft base of the bipolar transistor and an n.sup.+ region 15 constituting a collector leading-out region are formed.
Then, a heat treatment is conducted under an appropriate condition so that an emitter 32 is formed, as shown in FIG. 3D.
Succeedingly, a silicide film 33 is formed on the surface of the semiconductor substrate 1, and thereafter, an interlayer insulator 16 is formed. Contact holes arc formed at predetermined positions to penetrate through the interlayer insulator 16, and filled up with a conductive material if necessary, so that a source electrode 26. a drain electrode 27, a base electrode 28, an emitter electrode 29 ad a collector electrode 30 are formed at predetermined positions, respectively. Thus, a BiCMOS semiconductor device is formed.
Second Prior Art Method
FIGS. 4A to 4C are diagrammatic sectional views of a semiconductor device for illustrating the second prior art method for manufacturing the BiCMOS semiconductor device. In FIGS. 4A to 4C, elements similar to those shown in FIGS. 3A to 3D are given the same Reference Numerals, and explanation thereof will be omitted for simplification of the description.
In the second prior art method, as shown in FIG. 4A, after an insulator film 2 for a device isolation is formed in a predetermined area on a semiconductor substrate 1 (of for example a P-type) 1, an n.sup.+ region 4 of a high impurity concentration for leading out a collector region is formed in the semiconductor substrate 1, and then, an N-well (not shown) and a P-well 7 are formed.
Thereafter, an insulating film 6 is formed on the whole surface of the semiconductor substrate 1, and furthermore, a first polysilicon film 8 is formed on the whole surface of the insulating film 6. as shown in FIG. 4A.
Then, as shown in FIG. 4B, by using a photoresist (not shown) as a mask, a collector region 3 and a base region 5 of an NPN transistor are formed in predetermnied areas.
Furthermore, as shown in FIG. 4C, by a photolithography using a photoresist (not shown), an opening is formed to penetrate through the first polysilicon film 8 and the insulating film 6 at a predetermined position above the base region 5 so as to expose a portion of the base region 5. Succeedingly, a second polysilicon film 9 is formed on the whole surface including the opening thus formed, and an n-type impurity (for example, As) is introduced into the second polysilicon film 9.
Thereafter, the second polysilicon film 9 of the n type and the first polysilicon film 8 are patterned to be left in only respective predetermined areas of a MOS transistor formation area and a bipolar transistor formation area, so that a gate and an emitter are constituted. Incidentally, the step shown in FIG. 4C is the same as the step shown in FIG. 3B in the first prior art method.
After the step shown in FIG. 4C, the step shown in FIG. 3C in the first prior art method is carried out, so that the BiCMOS semiconductor device shown in FIG. 3D in the first prior are method is formed.
Incidentally, the above mentioned first and second prior art methods are different in that the first prior art method is characterized by folding the insulating film 6 (becoming the gate oxide film) after the base region 5 is formed (namely, by carrying out a thermal oxidation for formation of the gate oxide film of the MOS transistor after the base region 5 of the bipolar transistor is formed), and on the other hand, the second prior art method is characterized by forming the base region 5 after the insulating film 6 (becoming the gate oxide film) is formed (namely, by forming the base region 5 after the thermal oxidation for formation of the gate oxide film).
In addition, the second prior art method is different from the first prior method in that, after the first polysilicon film 8 is formed, the base region 5 is formed in order to protect the gate oxide film of the MOS transistors. In the other regards, both of the methods are composed of the same steps.
In the prior art methods for manufacturing the BiCMOS semiconductor device, exemplified by the above mentioned first and second prior art methods, the following various problems have been encountered.
A first problem is that: As in the above mentioned first and second prior art methods, since the prior art method for manufacturing the BiCMOS semiconductor device is constituted by incorporating a process for manufacturing a bipolar transistor into a process for manufacturing a MOS transistor, it is necessary to add masks and forming steps, so that the number of masks and steps are increased and the whole process becomes complicated.
The reason for this is that: The MOS transistor has been simplified for the purpose of reducing the cost, and incorporation of the bipolar transistor manufacturing process into the process for manufacturing a standard MOS transistor, results in a substantially difficult problem. For example, if it is attempted to incorporate the bipolar transistor manufacturing process into the standard MOS transistor manufacturing process, it is necessary to add masks and forming steps.
The number of added masks and steps has a relation to the performance of the device to be added. Although which of the bipolar transistor and the MOS transistor is added is dependent upon the purpose of the addition, if it is attempted to ensure the performance of both the devices, both of the number of added masks and the number of added forming steps will increase correspondingly.
A second problem is that in the above mentioned first prior art method, after the base region 5 of the bipolar transistor is formed, the insulating film 6 constituting the gate oxide film of the MOS transistor is formed, but the BiCMOS transistor manufactured by this method cannot have a high performance bipolar transistor.
The reason for this is that: Since in the first prior are method the insulating film 6 constituting the gate oxide film of the MOS transistor is formed after the base region 5 of the bipolar transistor is formed, the surface impurity or carrier concentration of the base region of the bipolar transistor remarkably drops because of the thermal oxidation for formation of the gate oxide film, as shown in, FIGS. 5A and 5B, with the result that a collector-emitter breakdown voltage remarkably drops.
FIGS. 5A and 5B are graphs showing the relation between the carrier concentration and the depth measured from the base region surface in the first prior art method in which the thermal oxidation for formation of the gate oxide film is carried out after the base region is formed. FIG. 5A illustrates the carrier concentration profile just after the doping for forming the base region is completed, and FIG. 5B illustrates the carrier concentration profile just after the thermal oxidation for forming the gate oxide film is completed. In FIGS. 5A and 5B. and in succeeding FIGS. 6 and 7, the carrier concentration is expressed by logarithms of the carrier concentration to the base ten (log base 10 of the carrier number per cm.sup.3). Therefore, in these figures, for example, "19" means 10.sup.19 cm.sup.-3. From comparison between FIGS. 5A and 5B, it would be seen that the surface concentration of the base region remarkably drops because of the thermal oxidation for formation of the gate oxide film.
In order to avoid the drop of the surface carrier concentration of the base region, it may be considered to enlarge the thickness of the base region in a vertical direction, namely, in a base region depth direction. However, this becomes a fatal problem in a technical approach of elevating the performance of the bipolar transistor by forming a shallow junction.
A third problem is that the first prior art method cannot realize a microminiaturization. The reason for this it that the drop of the collector-emitter breakdown voltage is more remarkable in an edge portion of the base region (namely, a junction portion between the base region and the insulator film for the device isolation), and therefore, it is necessary to make a distance between the emitter and the device isolation insulator film larger than a certain minimum distance, with the result that the microminiaturization is restricted by the minimum distance which must be ensured between the emitter and the device isolation insulator film. If this minimum distance between the emitter and the device isolation insulator film is not ensured, the yield of production remarkably drops because of the drop of the breakdown voltage.
In order to avoid the above problems, it has been known to form the base region after the thermal oxidation for formation of the gate oxide film, as in the second prior art method. In the second prior art method, however, in order to protect the gate oxide film for the MOS transistor, it is necessary to form the collector region 3 and the base region 5 after the first polysilicon film 8 is formed, as in the step shown in FIG. 4B. For this purpose, it is also necessary to increase an energy for an ion implantation, with the result that the base thickness in the vertical direction inevitably becomes large, as shown in FIG. 7, and therefore, a high performance bipolar transistor cannot be obtained.
FIG. 7 is a graph showing the relation between the carrier concentration and the depth measured from the base region surface in the second prior art method in which the base region is formed after the first polysilicon film is formed. From the base impurity concentration profile shown in FIG. 7. it would be understood that the base thickness (in the depth direction of the base region) is increased because of a high energy ion implantation.